This invention relates to a semiconductor memory device, and, particularly, relates to a dynamic type semiconductor memory device in which memory cells, each comprising one MOS transistor and one capacitor, are integrated on a substrate, and which requires a refreshing operation.
Of the various types of semiconductor memory devices, a dynamic random access memory (DRAM), in which each memory cell comprises one MOS transistor and one capacitor, has a simpler structure and is therefore leading the others, in terms of integration. However, the higher the integration, the smaller the capacitance of the capacitor, which would make it difficult to keep improving the integration in memories of 1 Mbits, 4 Mbits, and so forth, while maintaining the necessary capacitance of the capacitor.
With this situation in mind, a grooved structure, which has grooves formed in the substrate and provides a capacitance utilizing the walls of the grooves, becomes more advantageous for the capacitor than a conventional planar structure. The grooved structure includes CCC (Corrugated Capacitor Cell) and FCC (Folded Capacitor Cell) structures. With the use of these structures, the capacitance of a cell can be increased without increasing the cell area; that is, the cell area can be reduced without reducing the cell capacitance, thus contributing to a higher integration of a semiconductor memory device.
FIG. 1 shows the main portion of a conventional DRAM. A sense amplifier 10 comprises MOSFETs Q12 and Q14, which constitute a flip-flop, an activating MOSFET Q16, and an active restore circuit 18. A pair of bit lines BL and BL are coupled to the respective input terminals of the flip-flop of sense amplifier 10. Each of the bit line pair BL and BL is coupled with n/2 memory cells (n: the number of memory cells in one row) and a single dummy cell. For simplicity, however, FIG. 1 shows a single memory cell 20 and a single dummy cell 22, which are coupled to each bit line.
Memory cell 20 comprises a switching MOSFET Q24 and a cell capacitor C26, while dummy cell 22 comprises a switching MOSFET Q28 and a cell capacitor C30. The memory cell capacitor C26 has the aforementioned grooved structure, and the dummy cell capacitor C30 has a planar structure.
The output of a word line driver 32 is supplied to the gate of switching MOSFET Q24 of memory cell 20 through an equivalent word line delay circuit 34 (a delay of .tau.1). Similarly, the output of dummy cell driver 36 is supplied to the gate of switching MOSFET Q28 of dummy cell 22 through delay circuit 38 (a delay of .tau.1). The output of word line driver 32 is supplied to word line level detector 42 through dummy word line delay circuit 34 (a delay of .tau.1). The output of level detector 42 is supplied to the gate of activating MOSFET Q16 of sense amplifier 10 as well as to a CAS circuit (not shown).
A voltage of 0 V is applied to memory cell 20 to write "0" there, and a voltage of 5 V is applied to the memory cell to write "1". When dummy cell capacitor C30 has the same capacitance as memory cell capacitor C26, a voltage of 2.5 V is applied to dummy cell 22 to write "1" there, and, when the dummy cell capacitor has a half of the capacitance of the memory cell capacitor, a voltage of 0 V is applied to the dummy cell to write "1".
The operation of the conventional memory device in which data "0" is stored in memory cell 20 will now be explained with reference to FIG. 2, which illustrates a voltage change at each node shown in FIG. 1.
When word line driver 32 is driven, the voltage at its output node N25 rises. With a delay of .tau.1 after the voltage rising, the gate of switching MOSFET Q24 of memory cell 20 is opened, transferring the data in memory cell capacitor C26 on the bit line BL (node N21). At the same time, the data in dummy cell capacitor C30 is transferred on the bit line BL (node N22). Then, dummy word line delay circuit 40 and level detector 42 are activated, thus opening the gate (node N24) of activating MOSFET Q16 of sense amplifier 10. Consequently, the voltage at node N23 of sense amplifier 10 is discharged by MOSFET Q16, which starts the sensing operation. Sense amplifier 10 can output sense data when the voltage at node N23 becomes zero. Here, it is desirable to gradually discharge the voltage at node N23 in order to prevent a malfunction of sense amplifier 10; however, if the discharging is too slow, memory access would also be slow.
The discharging speed of the voltage at node N23 has the following correlation with the accuracy of the operation of sense amplifier 10. Sense amplifier 10 amplifies the potential difference SIG (=kCs) between nodes N21 and N22, where k is a constant and Cs is the capacitance of memory cell capacitor C26. The sensitivity S of sense amplifier 10, which corresponds to the minimum potential difference that sense amplifier 10 can detect and amplify, is given as: EQU K.sqroot.(dv/dt).times.(.DELTA..beta./.beta.+.DELTA.Cl/Cl)+.DELTA.Vt,
where K.sqroot.(dv/dt) is the operation speed (sensing speed) of the sense amplifier (i.e., the discharging speed of the voltage at node N23), .DELTA..beta./.beta. is the difference in conductance between MOSFETs Q12 and Q14, .DELTA.Cl/Cl is the difference in capacitance between bit lines BL and BL, and .DELTA.Vt is the difference in threshold values between MOSFETs Q12 and Q14. Sense amplifier 10 accurately functions when SIG&gt;S, but malfunctions when SIG.ltoreq.S.
When the capacitance of memory cell capacitor C26 is small, the potential difference SIG between nodes N21 and N22 before the sensing operation becomes significantly small. In this case, if the conductance (current driving ability) of MOSFET Q14 is larger than that of MOSFET Q12, which constitutes a flip-flop together with MOSFET Q14, then MOSFET Q14 is turned on first, and, as a consequence, the relationship between the levels of the voltages at nodes N21 and N22 is reversed, resulting in an erroneous data readout.
To prevent such an erroneous operation, the sensitivity S of the sense amplifier needs to be smaller than SIG (potential difference between nodes N21 and N22) even when the memory cell capacitor has a minimum capacitance. It is the sensing speed K.sqroot.(dv/dt) in the sensitivity S which can actually be decreased, and this sensing speed should be decreased (or slower) in order to prevent a malfunction of the sense amplifier. However, since the memory cell capacitance of a memory device produced with typical process parameters is likely to be slightly larger than the minimum value, if the sensing speed K.sqroot.(dv/dt) is fixed to the minimum according to the expected minimum value of the memory cell capacitance, the sensing speed would be unnecessarily slow.